1. Field of the Invention
The present invention generally relates to a packet transfer system for assembling logically multiplexed ATM (Asynchronous Transfer Mode) cells into a packet and for transmitting the packet to a destination logical channel according to packet header information. More particularly, the present invention relates to a packet transfer system adapted to separate and couple a transfer performed by hardware processing and a transfer performed by software processing.
In recent years, a demand for increasing the packet transfer rate of a packet transfer system has occurred with the increase in packet traffic in an ATM network that transfers an IP (Internet Protocol) packets. Implementation of a packet transfer process consisting of a series of steps of assembling a packet, retrieving transfer destination information, and transmitting a packet by hardware has been promoted to ensure the demand. On the other hand, concurrently, there has been an increase in traffic of high-level protocol packets requiring the implementation of a packet transfer process by software. Thus, there has been a demand for enhancement of the throughput of the packet transfer process implemented by software, in addition to the demand for increasing the packet transfer rate by the implementation of the packet transfer process by hardware.
Consequently, there is a need for providing a coupling device which prevents the throughput of the packet transfer process implemented by hardware and the throughput of the packet transfer process implemented by software from affecting each other and for an auxiliary device that assists the packet receipt and transmission implemented by software.
2. Description of the Related Art
FIG. 1 illustrates the arrangement of packet transfer modules, to which the packet transfer system of the present invention is applied, in a network.
A plurality of packet transfer modules are placed in an ATM network. These packet transfer modules are connected to one another and to routers of user networks through multiplexers. The packet transfer modules, the multiplexers, and the routers are connected to one another through ATM interfaces. A packet transmitted from each of the user networks is xe2x80x9cATM-cellizedxe2x80x9d (in the present specification, the expression xe2x80x9cATM-cellizedxe2x80x9d means xe2x80x9cassembled in a format of an ATM cell without disassembling ATM cells) by using the AAL type 5 format in the router. Then, the ATM cells transmitted from a plurality of user networks are multiplexed in the multiplexer that accommodates lines connected to a plurality of routers. Subsequently, the multiplexed ATM cells are inputted from this multiplexer to a packet transfer module.
The packet transfer module assembles the inputted ATM cells into a packet, and then retrieves a destination address from a packet header. Subsequently, the packet transfer module transmits the packet according to the destination address, which is obtained as a result of the retrieval, to a destination user network connected to a line accommodated by this transfer module itself or to another packet transfer module that accommodates a line connected to a destination user network. Meanwhile, if no destination is found as a result of the retrieval of the destination address from the packet header in the packet transfer module, this packet is terminated according to the protocol at this packet transfer module itself or, if the packet violates the protocol, the packet is not transferred but terminated at this module itself.
FIG. 2 is a diagram illustrating a principle of a conventional packet transfer system.
In this figure, reference numeral 30 designates a packet assembling/transmitting portion for receiving an ATM cell from a circuit and for transmitting an ATM cell to a circuit. Reference numeral 31 denotes a buffer memory for storing a packet to be transmitted and received. Reference numeral 32 designates a higher layer processing portion for processing header information of a packet. Reference numeral 33 denotes a processor (namely, a software processing portion) for performing software processing on a predetermined packet.
When receiving a logically multiplexed ATM cell from a circuit, the packet assembling/transmitting portion 30 disassembles the received ATM cells while the higher layer processing portion 32 retrieves a transfer destination according to a packet header and performs packet validation or verification. Then, the packet assembling/transmitting portion 30 assembles a packet and causes the buffer memory 31 to store the assembled packet. In the case that the transfer destination is determined by the higher layer processing portion 32, the packet stored in the buffer memory 31 is assembled by the packet assembling/transmitting portion 30 into a cell without software processing performed by the processor 33. Then, this cell is transmitted to the circuit.
Conversely, in the case that the implementation of the packet transfer process by hardware cannot be achieved because the transfer destination is not determined by the higher layer processing portion 32, the software processing portion 33 is notified of the packet reception. Thus, the software processing portion 33 reads this packet from the buffer memory 31 and analyzes a primary factor in transfer of the packet. Consequently, the software processing portion 33 determines the next processing to be performed.
In the case that the software processing portion 33 transmits a packet, the software processing portion 33 retrieves a destination, to which the packet is to be transferred, by using a destination retrieval table 34. Then, the software processing portion 33 writes a packet, which is to be transmitted, to the buffer memory 31 after a transfer destination is determined. Subsequently, the software processing portion 33 notifies the packet assembling/transmitting portion 30 to thereby instruct the portion 30 to transmit a packet. The packet assembling/transmitting portion 30, which is instructed to transmit the packet, assembles the packet, which is stored in the buffer memory 31, into a cell and then transmits this cell to the circuit. In this packet transfer system, accesses to the buffer memory 31 from the hardware (namely, the packet assembling/transmitting portion 30) and the software (namely, the software processing portion 33) are achieved by using the same path 35 during contention arbitration is performed.
Thus, in the case of the conventional packet transfer system, when receiving an ATM cell, a packet is assembled and stored in the buffer memory during the transfer destination retrieval and the packet validation are performed by hardware processing. In the case that the transfer destination is determined, the packet stored in the buffer memory is transmitted without software processing. Meanwhile, a packet, which needs to undergo software processing owing to the fact that the transfer destination is not determined, is received by accessing a buffer memory that is the same as the buffer memory used in the transfer implemented by hardware.
In this case, the software needs to analyze the factor that the packet is transferred, and to determine the next processing to be performed. Further, when a packet is transmitted from the software, the packet is prepared in the buffer memory and transmitted by accessing this buffer memory that is the same as a buffer memory used in the transfer implemented by the hardware. Moreover, the software needs to perform an operation of preliminarily retrieving and determining a transfer destination according to destination information of a packet.
In such a conventional packet transfer system a bus contention between an access to the buffer memory by the hardware and an access thereto by the software occurs. Thus, an increase in the number of circuits used by the software for accessing the buffer memory suppresses an access thereto by the hardware. Consequently, there has been caused a problem that the throughput of the transfer by the hardware is degraded.
Further, in the case that the priority of accesses to the buffer memory by the hardware is set in such a manner as to be higher than the priority of accesses thereto by the software, and that limitation is imposed to the circuits used by the software for accessing the buffer memory, the throughput of the transfer implemented by the software is degraded.
Moreover, the software is required to determine the kind of a protocol, according to which a packet is transferred, and to analyze a primary factor in occurrence of errors. Furthermore, in the case of the transfer of a packet, which is implemented by the software, there is the necessity for preliminarily retrieving a destination by the destination retrieval table. The processing load, in such a case, is one of factors that degrade the throughput of the software.
The present invention is accomplished in view of the aforementioned problems and the recent technology trends of the packet transfer system. Accordingly, an object of the present invention is to realize a high-speed packet transfer by implementing a packet transfer process by hardware and to enhance the throughput of the packet transfer process implemented by software.
Further, another object of the present invention is to increase the capacity of a packet transfer system by providing a device for coupling a plurality of packet transfer systems to one another.
(1) To achieve the foregoing objects, according to an aspect of the present invention, there is provided a packet transfer system that has a packet transfer device including a hardware processing portion. This device has an expansion circuit, which is connected to a software processing portion, in addition to a main circuit to be connected to an external system. A packet to be transmitted to the main circuit is read from a buffer memory and then transmitted thereto. A packet required to undergo software processing is read by the hardware processing portion itself and transmitted to the software processing portion through the expansion circuit. Further, in the buffer memory of the hardware processing portion, a packet is assembled by using an ATM cell without disassembling the ATM cell. Consequently, a buffer pointer control operation is simplified. Furthermore, an independent buffer memory for software processing is provided therein. Thus, the software processing, which is relatively slowly performed and involves frequent memory accesses for header rewriting and descriptor processing, is performed by using this buffer memory.
(2) The packet transfer system of the present invention is adapted so that the hardware processing portion writes a packet, which is received from the main circuit, to the buffer memory thereof and assembles a packet in this buffer memory, and that the software processing portion receives from the expansion circuit the packet that is transmitted to the expansion circuit by the hardware processing portion. Thus, the hardware processing portion itself writes a packet to the buffer memory and assembles a packet therein. Consequently, the hardware processing portion receives from the software processing portion, through the expansion circuit, concurrently with reception of cells from the main circuit without causing the cells to wait to be received.
(3) The hardware processing portion sends packet header information to the higher layer processing portion upon completion of assembling of a packet or a packet header portion. Then, the higher layer processing portion performs higher layer processing, such as packet validation and destination retrieval, according to packet header information, and determines the kind of the circuit and a logical channel according to a result of the higher layer processing. When a result reveals that the packet should be transmitted according to a preset protocol, the hardware processing portion transmits this packet to the software processing portion.
(4) Regarding accesses to the buffer memory of the hardware processing portion, an access thereto at reception of an ATM cell from the main circuit and an access thereto at reception of an ATM cell from the expansion circuit are performed, independently of each other, in the packet assembling portion at the cell-receiving side. Alternatively, both of such accesses to thereto are performed in common by a multiplexer. Further, the transmission of a packet to the main circuit and the transmission of a packet to the expansion circuit are performed independently of each other in the packet determining/transmitting portion at the cell-transmitting side. Alternatively, both of such transmissions are performed in common by a demultiplexer.
(5) In the case that the hardware processing portion transmits packets to the software processing portion through the expansion circuit, packet type identifiers or codes are distributed to the logical channels. Further, information on a result of the higher layer processing performed in the hardware processing portion is attached to the packet as detail information. When receiving this packet, the software processing portion determines the next processing, which is to be performed, according to the logical channel corresponding to and the detail information attached to the received packet. This eliminates the necessity for performing packet analysis processing therein, which is redundant in view of the packet analysis processing performed in the hardware processing portion.
(6) The hardware processing portion monitors the congestion state of the buffer memory in the software processing portion. When a congestion state of the common receiving buffer memory occurs, the software processing portion is controlled in such a manner as to wait for a transmission of a packet dequeued from the entire transmission queue for the expansion circuit at the side of the hardware processing portion. Conversely, when a congestion state of a receiving buffer memory corresponding to a certain logical channel at the side of the hardware processing portion is caused, the software processing portion is controlled in such a way as to wait for a transmission of a packet dequeued from all transmission queues corresponding to this logical channel at the side of the hardware processing portion. This prevents the hardware processing portion from transmitting a packet, whose priority for undergoing software processing is low, to the software processing portion. Consequently, an occurrence of buffer overflow in the software processing portion is prevented. Moreover, the need for congestion control in the software processing portion is eliminated.
(7) In the case that the software processing portion transmits a packet, whose transmission destination is not designated by software, the hardware processing portion performs transmission destination retrieval. Then, the packet is transmitted to a transmission destination obtained as a result of the retrieval. Consequently, the necessity for performing transmission destination retrieval by the software processing portion is eliminated. Thus, IP table retrieval by software becomes unnecessary.
(8) On the other hand, when it is not desired that the retrieval is performed in the hardware processing portion, a transmission destination is preliminarily retrieved by software in the software processing portion and then a packet, whose transmission destination is thus designated, is transmitted to the hardware processing portion through the expansion circuit. In this case, the packet is transmitted to the designated transmission destination without performing transmission destination retrieval in the hardware processing system. Thus, the package can be transmitted to a transmission destination, which is arbitrarily designated by the software processing portion, by the hardware processing portion.
(9) The software processing portion divides the transmission queue for the main circuit into a plurality of parts respectively corresponding to packet types. Moreover, the software processing portion divides the transmission queue for the expansion circuit into a plurality of parts respectively corresponding to packet types. Furthermore, transmission scheduling is performed among packets contained the transmission queues corresponding to the main circuit or the transmission queues corresponding to the expansion circuit or all of these transmission queues. Additionally, packets are transmitted by enabling the setting of a priority corresponding to each of packet types. Consequently, the software processing portion can preferentially receive a packet of a high priority.
(10) Further, the packet transfer system of the present invention has a plurality of packet transfer devices each constituted by a hardware processing portion, which are connected to a single software processing portion. Thus, the system is adapted so that the plurality of hardware processing portions, that is, packet transfer devices, which are appropriate to the throughput of the software processing portion, can be connected to the software processing portion.
(11) Furthermore, this packet transfer system is adapted so that a packet, whose transmission destination is not obtained by performing higher layer processing in a hardware processing portion, can be transmitted to another hardware processing portion through a second expansion circuit, and that each of hardware processing portions can receive a packet from the second expansion circuit. Thus, in the case that each hardware processing portion cannot obtain a transmission destination of a packet in an own higher layer processing portion, the transmission destination is retrieved by another higher layer processing portion. Consequently, a packet received by one of the packet transfer devices can be transmitted from another of the packet transfer devices.